With an LSI, as further progress has been made in micro-fabrication technology, so a greater number of transistors have been integrated on one chip, having thereby attempted to achieve enhancement in performance. However, due to limitations to miniaturization, an increase in cost of utilizing a leading-edge process, and so forth, it will not necessarily provide the optimal solution to a problem to promote further integration of the transistors on one chip as in the past. Accordingly, integration in three-dimensional directions, implemented by piling up a plurality of LSIs, will become a technology that is highly hoped for.
In order to obtain a desired performance of stacked LSIs, communication function among LSIs piled up one after another is important. One of favorite solutions to a problem of the communication system for the stacked LSIs is multiple-pin 3D communication by use of a silicon penetration-electrode. Thus, in JP-A-2007-158237, use is made of a bus-connection system whereby circuits on a plurality of LSIs have authority for outputting to a specific penetration-electrode, as a system for making connection among the stacked LSIs through the intermediary of the silicon penetration-electrode.